The increasing complexity of integrated circuits has forced integrated circuit designers to develop pipelined components that connect one component to the other. In many integrated circuits various high-speed processors are connected to slower memory units. The processors and the memory units can be connected to different buses that have different widths, different clock signal frequencies as well as other optional characteristics.
Cache memory units, speculative fetch operations and predictive fetch operations were introduced in order to reduce timing penalties resulting from relative slow data retrieval operations. Speculative fetch operation as well as predictive fetch operations involve fetching information that was not explicitly requested by the processor.
Various fetch requests are usually generated by a processor and sent to the memory unit. The memory unit (or a memory unit access controller) may acknowledge these fetch requests and then send the requested information to the processor or to a cache memory unit.
In some cases a speculative (or predictive) fetch operation provides useful information that is used by the processor but in some cases the speculative (or predictive) fetch operations provide information that is not used by the processor, especially when the processor deviated from a previously estimated program progress.
FIG. 1 illustrates a prior art timing diagram 100 that illustrates various access requests, access requests acknowledge events and retrieved information units.
Timing diagram 100 illustrates a burst of four consecutive access requests (RX1-RX4 101-104) generated by a master component at times T1-T4. These access requests are acknowledged by a burst of four consecutive access acknowledgments (TX1-TX4 111-114) at times T2-T5. The acknowledged access requests are sent over a pipelined slave bus towards a slave component.
Assuming that neither of these acknowledged access request is timely cancelled the slave component provides information units IU1-IU4 121-124 during eight cycles (that start at T7-T14). Each information unit is sent to the master component during two beats. Thus, during times T7-T14 the master component receives information chunks IC_1,1 121(1), IC_1,2 121(2), IC_2,1 122(1), IC_2,2 122(2), IC_3,1 123(1), IC_3,2 123(2), IC_4,1 124(1) and IC_4,2 124(2).
RX4 104 can be cancelled (before being acknowledged) until T4. Thus, only a narrow time window (of three access controller cycles) is provided for a simple cancellation of the speculative access request.
It is further noted that some device do not allow to cancel an acknowledged access request, thus even if the fetched information will not be useful, the device will have to service the access request.
There is a need to provide a device and method for managing data access requests.